1. Field of the Invention
The present invention relates to a method for fabricating a MOSFET device, and more particularly to a MOSFET fabrication method capable of allowing application of a self-aligned contact process while maintaining a metal gate to have a uniform thickness.
2. Description of the Related Art
It is well known that gates of transistors are mainly made of polysilicon. This is because polysilicon sufficiently meets desired properties required for gates such as a high melting point, ease of forming thin films, ease of patterning lines, stability in an oxidation atmosphere, and formation of planarized surfaces. Further, where polysilicon gates are applied to MOSFET devices, a desired resistance can be obtained by doping the gate with impurities such as phosphorous (P), arsenic (As), or boron (B).
As the level of integration of semiconductor devices increases, parameter values of the device correspondingly are affected. For example, the line width of gates, the thickness of gate insulating films, and the junction depth decrease. For this reason, where highly integrated semiconductor devices are fabricated using polysilicon, it is difficult to realize a low resistance required in association with the decrease in the micro line width. Thus, it is required to develop gates made of a new material as a substitute for polysilicon.
Active research and development efforts have been made in association with polycide gates made of a transition metal-silicide material. However, such polycide gates also have a limitation in realizing a low resistance since polysilicon remains a part of the gate material. Semiconductor devices having a polycide gate involve an increase in the effective thickness of a gate insulating film due to a gate depletion effect resulting from polysilicon present in the polycide gate. Also, there may be a variation in threshold voltage resulting from boron penetration and dopant distribution fluctuation occurring in a p+ polysilicon gate. For this reason, use of polycide to achieve low resistance gates is limited.
To this end, active research and development have recently been made in association with metal gates. Metal gates solve the above-mentioned problems involved in semiconductor devices using polycide gates because they do not use any dopant. Also, if the metal gate is made of a metal having a work function value corresponding to the mid band-gap of silicon, it can be fabricated into a single gate usable for both the NMOS and PMOS types. The metal having a work function value corresponding to the mid band-gap of silicon include tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), molybdenum (Mo), tantalum (Ta), and tantalum nitride (TaN).
Unfortunately, such metal gates have problems as well. When manufacturing MOSFET devices with such metal gates, there are processing difficulties. These difficulties include difficulty in etching associated metal films, damage to the silicon substrate during the etching process, and thermal damage resulting from a thermal process conducted following the etching process.
For these reasons, it is difficult to form a metal gate using conventional gate formation processes. To this end, a method has been proposed in which metal gates are formed using a damascene process, which is mainly used in the formation of metal lines.
The metal gate formation method using the damascene process involves forming a transistor including a sacrificial gate made of polysilicon, forming an interlayer insulating film, removing the sacrificial gate, depositing a metal film, and conducting a chemical mechanical polishing (CMP) process for the metal film. Since this method does not involve etching when forming the metal gate, it avoids degradation in the characteristics of the final product while allowing the use of conventional MOSFET process.
A conventional metal gate formation method using a damascene process will be described in conjunction with FIGS. 1A to 1E. Referring to FIG. 1A, field oxide films 2 are formed on a silicon substrate 1 to define an active region. A first thermal oxide film 3 is formed on the silicon substrate 1 to cover the active region. Thereafter, a polysilicon film 4 and a hard mask film 5 are sequentially deposited on the field oxide film 2 and first thermal oxide film 3.
Referring to FIG. 1B, a hard mask pattern 5a defining a gate formation region is formed by patterning the hard mask film 5 by photolithography. The polysilicon film 4 and first thermal oxide film 3 are then etched (no metal gate has been formed yet) using the hard mask pattern 5a as an etch mask. As a result, a first intermediate structure is formed including a sacrificial gate 4a. 
The first intermediate structure is subjected to a gate re-oxidation process, so that a second thermal oxide film 6 is formed on the sides of the sacrificial gate 4a and the exposed surface of the silicon substrate 1. Subsequently, impurity ions are implanted in low concentrations into portions of the silicon substrate 1 on both sides of the sacrificial gate 4a through the second thermal oxide film 6. As a result, lightly doped drain (LDD) regions 7 are formed.
Referring to FIG. 1C, the second thermal oxide film 6 is then removed. Thereafter, spacers 8 are formed on sides of the sacrificial gate 4a, the hard mask pattern 5a, and the remaining thermal oxide 3. Impurity ions are then implanted in high concentrations into portions of the silicon substrate 1 again on both sides of the sacrificial gate 4a including the spacers 8. As a result, a second intermediate structure is formed including source/drain regions 9.
Referring to FIG. 1D, an interlayer insulating film 10 is deposited on the second intermediate structure obtained after completion of the processing steps shown in FIG. 1C. Thereafter, the interlayer insulating film 10 and the hard mask pattern 5a are polished using a CMP process with the sacrificial gate 4a acting as a polishing stop layer at point where the sacrificial gate 4a is exposed. Then the sacrificial gate 4a and the first thermal oxide film 3 disposed beneath the sacrificial gate 4a are removed to define a groove, thereby forming a third intermediate structure. A metal gate is later formed in the groove.
A uniformly thick gate insulating film 11 is formed on the third intermediate structure. Subsequently, a tungsten film 12 is deposited on the gate insulating film 11 so that it completely fills the groove.
Referring to FIG. 1E, a tungsten gate 12a is then formed by polishing the tungsten film 12 and gate insulating film 11 using a CMP process with the interlayer insulating film 10 acting as a polishing stop layer.
Since the tungsten gate 12a is formed using a damascene process, as mentioned above, it has a desired reliability. Accordingly, the MOSFET device having the tungsten gate 12a can be expected to have improved characteristics.
However, this MOSFET device having the tungsten gate 12a is subjected to degradation in characteristic due to a self-aligned contact (SAC) process that is subsequently conducted. This is because there is no barrier film for the SAC process. Multiple processing steps are necessary to form a SAC barrier film. The additional steps are disadvantageous in terms of productivity.
Problems involved in the above mentioned SAC process will now be described in detail, with reference to FIGS. 2 and 3. Here, the SAC process and the SAC barrier film formation process are well known, so that their description are omitted. In FIGS. 2 and 3, the reference numeral 13 denotes a SAC barrier film, 14 an insulating film, and 15 a contact plug.
When a misalignment occurs, as shown in FIG. 2, an electrical short circuit may result between the tungsten gate 12a and the contact plug due to the lack of the SAC barrier film on the tungsten gate 12a. Thus, the reliability and other characteristics of the MOSFET device are compromised.
The electrical short circuit between tungsten gate 12a and contact plug 15 may be avoided by forming a SAC barrier film 13 made of, for example, a nitride film, on the tungsten gate 12a. However, the formation of the SAC barrier film 13 requires an increase in the manufacturing time and therefore costs of the MOSFET device because the film necessarily involves the additional process of etching the tungsten gate, depositing a nitride film, and polishing the nitride film. Consequently, productivity is reduced.
An important factor to be taken into consideration in the manufacture of MOSFET devices is to maintain the surface resistance of the gate to be at or below an acceptable maximum level. Here, the surface resistance of the gate depends on the thickness uniformity of the gate.
However, where the tungsten gate is etched at its surface to have a reduced thickness in accordance with a dry etching process, it may not have a desired thickness uniformity after completion of the etching process since there is no etch stop layer. In particular, it is difficult to etch all tungsten gates distributed throughout the substrate to have a uniform etch depth.
Furthermore, if the etching device is unstable, the tungsten gate will be either excessively or insufficiently etched. Then it becomes impossible to maintain a desired thickness uniformity of the tungsten gate. If such is the case, the tungsten gate may have a surface resistance exceeding the acceptable threshold value. As a result, the MOSFET device may exhibit degraded characteristics.
Therefore, an object of the invention is to provide a MOSFET fabrication method capable of allowing application of a SAC process while maintaining a tungsten gate to have a uniform thickness.
In accordance with the present invention, this object is accomplished by providing a method for fabricating a MOSFET device comprising: forming field oxide films on a prepared substrate defining an active region; forming a sacrificial gate on the active region; forming a lightly doped drain (LDD) source/drain regions in the substrate on both sides of the sacrificial gate and forming an interlayer insulating film on a resulting structure; removing the sacrificial gate to define a groove region where a metal gate is to be formed; forming a gate insulating film on the interlayer insulating film and in the groove region; depositing a metal film on the gate insulating film and filling the groove region; polishing the metal film and the gate insulating film thereby leaving the metal film in the groove forming the metal gate; and oxidizing the metal gate thereby forming a metal oxide film having a desired thickness on the surface of the metal gate.
In another aspect of the invention, the object of the invention is accomplished by a method comprising: forming a sacrificial gate structure on an active region of a substrate; forming LDD regions in the substrate on both sides of the sacrificial gate in the active region using the sacrificial gate structure as a mask; forming spacers on the sides of the sacrificial gate; forming HDD regions in the substrate on both sides of the sacrificial gate in the active region using the sacrificial gate structure and the spacer as a mask; depositing an interlayer insulating film on the active region of the substrate and on the sacrificial gate structure; polishing the interlayer insulating film exposing the sacrificial gate structure; removing the sacrificial gate structure forming a groove such that spacers define sides of the groove and the substrate is exposed within the groove; depositing a gate insulating film in the groove such that the groove is not completely filled; forming a metal gate by depositing a metal film in a remainder of the groove; and forming a metal oxide on the metal gate.
In a further aspect of the invention, the object of the invention is accomplished by a device comprising: a substrate; at least two field oxide films defining an active region on the substrate; a metal gate formed over the substrate within the active region with a metal oxide SAC barrier film at a top of the metal gate; lightly doped source and drain regions formed in the substrate on both sides of the metal gate; and heavily doped source and drain regions formed in the substrate on both sides of the metal gate.